Alif Semiconductor /AE302F80F5582LE_CM55_HE_View /ETH /ETH_MAC_PPS_CONTROL

Pulse Per Second (PPS) Frequency Control This field controls the PPS frequency. The default value of PPSCTRL is 0x0, and the PPS frequency is 1 pulse every second. For other values of PPSCTRL, the PPS becomes a generated clock of the following frequencies: Note: In the binary rollover mode, the PPS frequency has a duty cycle of 50 percent with these frequencies. In the digital rollover mode, the PPS frequency is an average number. The actual clock is of different frequency that gets synchronized every second. For example: When PPSCTRL = 0x1, the PPS (1 Hz) has a low period of 537 ms and a high period of 463 ms When PPSCTRL = 0x2, the PPS (2 Hz) is a sequence of:

• One clock of 50 percent duty cycle and 537 ms period
• Second clock of 463 ms period (268 ms low and 195 ms high) When PPSCTRL = 0x3, the PPS (4 Hz) is a sequence of:
• Fourth clock of 195 ms period (134 ms low and 61 ms high) This behavior is because of the non-linear toggling of bits in the digital rollover mode in the ETH_MAC_SYSTEM_TIME_NANOSECONDS register.

1 (Val_0x1): The binary rollover is 2 Hz, and the digital rollover is 1 Hz.

2 (Val_0x2): The binary rollover is 4 Hz, and the digital rollover is 2 Hz.

3 (Val_0x3): The binary rollover is 8 Hz, and the digital rollover is 4 Hz.

4 (Val_0x4): The binary rollover is 16 Hz, and the digital rollover is 8 Hz.

15 (Val_0xF): The binary rollover is 32.768 kHz and the digital rollover is 16.384 kHz.